Communication systems use convolutional encoding of data for error detection and correction. The receiver of the communication system convolutionally decodes the encoded data to reconstruct the initial transmitted data. One well-known method of convolutional code decoding is the Viterbi algorithm. The Viterbi algorithm determines either the shortest or longest path to each current state from states that occur previously. A brute force method for such determination is to determine the length of all possible paths. This takes large amounts of memory, processing capability, and time. Instead, the Viterbi algorithm determines the current state from the previous state which is remembered and accumulates the data, called metrics. The Viterbi algorithm may be implemented either in hardware or software or both. Recently the Viterbi decoders have been implemented as application specific integrated circuits (ASIC) using very large integration (VLSI) technology. Tradeoffs between performance and cost in the hardware implementation is a very critical issue. Many different architectures have been used.
These architectures are inflexible in that their design does not provide simple scalability. It is desired to have a Viterbi decoder that allows expansion for increasing numbers of states and that allows a decoder architecture that can be fully parallel, fully serial, or partially parallel, partially serial.